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| T R I Q U I N T S E M I C ON D U C TO R, I N C. TGF4250-EEU 4.8 mm Discr ete HFET q q q q q q PHOTO ENLARGEMENT 4800 m x 0.5 m HFET Nominal Pout of 34- dBm at 8.5- GHz Nominal Gain of 8.5- dB at 8.5- GHz Nominal PAE of 53% at 8.5 - GHz Suitable for high reliability applications 4250 0,572 x 1,334 x 0,102 mm (0.023 x 0.053 x 0.004 in.) DESCRIPTION The TriQuint TGF4250-EEU is a single gate 4.8 mm discrete GaAs Heterostructure Field Ef fect Transistor (HFET) designed for high ef ficiency power applications up to 10. 5- GHz in Class A and Class AB operation. Typical performance at 2- GHz is 34 - dBm power output, 13 - dB gain, and 63% PAE. Bond pad and backside metalization is gold plated for compat ibility with eutectic alloy attach methods as well as thermocompr ession and thermosonic wire-bonding processes. The TGF4250-EEU is readily assembled using automatic equipment. TriQuint Semiconductor, Inc. * Texas Facilities * (972) 995-8465 * www.triquint.com TGF4250-EEU p EXAMPLE OF DC I-V CURVES 1.1 1 0.9 VG = 0.0 to -2.25 V (0.25 V steps) T A=65C Drain Current (A) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 Drain Voltage (V) OUTPUT POWER VS. INPUT POWER Output Power (dBm) 36 34 32 30 28 26 24 F =8.5 GHz VD =8.0 V I Q =200 mA* T A =25C 22 20 10 12 14 16 18 20 22 24 26 28 Input Power (dBm) * I Q is defined as the drain current before application of RF signal at the input. POWER ADDED EFFICIENCY VS. INPUT POWER 55 50 45 40 35 F =8.5 GHz VD =8.0 V I Q =200 mA T A =25C PAE (%) 30 25 20 15 10 5 0 10 12 14 16 18 20 22 24 26 28 Input Power (dBm) 2 TriQuint Semiconductor, Inc. * Texas Facilities * (972) 995-8465 * www.triquint.com TGF4250-EEU GAIN VS. INPUT POWER 11 F =8.5GHz VD =8.0V I Q =200 mA C T A =25 10 Gain (dB) 9 8 7 10 12 14 16 18 20 22 24 26 28 Input Power (dBm) DRAIN CURRENT VS. INPUT POWER 0.6 0.55 0.5 F =8.5GHz VD =8.0V I Q =200 mA C T A =25 Drain Current (A) 0.45 0.4 0.35 0.3 0.25 0.2 10 12 14 16 18 20 22 24 26 28 Input Power (dBm) ABSOLUTE MAXIMUM RATINGS Drain - to- source voltage, VDS ................................................................................................................ 12 V Gate - to- source voltage, VGS ........................................................................................................ -5 V to 0 V Mounting temperatur e (30 sec), TM .................................................................................................. 320 C Storage temperature range, TSTG ............................................................................................ - 65 to 200 C Power dissipation, PD ................................................................................. (see thermal data on next page) . Operating channel temperature, TCH ............................................................ (see thermal data on next page) Ratings over operating channel temperature (unless otherwise noted) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "RF and DC Characteristics" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. TriQuint Semiconductor, Inc. * Texas Facilities * (972) 995-8465 * www.triquint.com 3 TGF4250-EEU p PREDICTED CHANNEL TEMPERATURE VS. CARRIER BASE TEMPERATURE at 2.04 W and 4.08 W dissipated power 350 300 Channel Temperature ( C) 250 200 150 100 50 0 -50 -100 -50 0 50 100 150 200 2.04 W 4.08 W Carrier Base T emperature (C) 38 m AuSn solder attach to 0.5 mm CuMo Carrier. Channel Temperature ( C) HFET CHANNEL TEMPERATURE VS. MEDIAN LIFE 325 300 275 250 225 200 175 150 125 100 1 2 3 4 5 6 7 8 9 10 11415 years Median Life (10^X Hours) Median Life (10^ x Hours) TriQuint Semiconductor, Inc. * Texas Facilities * (972) 995-8465 * www.triquint.com 4 TGF4250-EEU RF AND DC CHARACTERISTICS PARAMETER MIN NOMINAL MAX UNIT Pout GP PAE IDSS GM VP BVGS BVGD Output Power Power Gain Power Added Efficiency Drain Saturation Current Transconductance Pinch Off Voltage Breakdown Voltage Gate-Source Breakdown Voltage Gate-Drain 33 7 47 816 576 -2.7 -30 -30 34 8.5 53 1176 792 -1.85 -22 -22 1536 1008 -1 -17 -17 dBm dB % mA mS V V V Pout, Gain, and P AE: Measured at 8.5- GHz, drain voltage of 8.0 V . Gate voltage is adjusted to achieve quiescent current of approximately 20% I DSS with no RF signal applied. The source is grounded. Input power between 25 and 26- dBm. I DSS : Saturated drain- source current. Sear ch for the maximum IDS at VGS = 0.0 V, and VDS swept between 0.5 V to 3.5 V. Note that the drain voltage at which I DSS is located and recorded as VDSP. GM : Transconductance. (I DSS - I DS1)/ I VG1 I. I DS1 measured at VG1 = - 0.25 V using the knee sear ch technique; VDS swept between 0.5 V and VDSP to search for maximum I DS1. VP : Pinch off voltage. VGS for I DS = 0.5 mA/mm of gate width. VDS fixed at 2.0 V, VGS swept to bring I DS to 0.5 mA/mm. Sweep will stop if VP current not found beyond 0.5 V of the minimum V P specification. BVGS : Breakdown voltage, gate to source. I BD = 1.0 mA/mm of gate width. Source fixed at ground, drain not connected (floating). When 1.0mA/mm drawn at gate, VGS measured as BVGS. BVGD: Breakdown voltage, gate to drain. I BD = 1.0 mA/mm of gate width. Drain fixed at ground, source not connected (floating). When 1.0 mA/mm drawn at the gate, VGD measured as BVGD. LINEAR MODEL R DG LG G RI R GS C GS R1 RG C DG V CCS RD LD D C DS R2 R DS RS LS VDS = 8.0 V and 30% I DSS at T = 25C FET Elements L G = 0.010525 nH R G = 0.21075 R GS = 20425 R I = 0.3025 C GS = 4.84 pF CDG = 0.4015 pF R DG = 51000 R S = 0.1 L S = 0.011 nH R DS = 24.5025 CDS = 1.013 pF R D = 0.165 L D = 0.0055 nH VCCS Parameters M = 531.6 mS A=0 R1 = 1E19 R2 = 1E19 F=0 T = 5.49 pS 5 TriQuint Semiconductor, Inc. * Texas Facilities * (972) 995-8465 * www.triquint.com TGF4250-EEU MODELED S -PARAMETERS Frequency (GHz) MAG S 11 S 21 S 12 S 22 ANG(o) MAG ANG(o) MAG ANG(o) MAG ANG(o) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 0.943 0.932 0.929 0.928 0.928 0.929 0.929 0.930 0.931 0.932 0.933 0.935 0.936 0.937 0.938 0.940 0.941 0.942 0.944 0.945 0.946 -106.98 -139.41 -152.35 -159.14 -163.31 -166.14 -168.18 -169.74 -170.97 -171.97 -172.82 -173.54 -174.17 -174.73 -175.23 -175.69 -176.12 -176.51 -176.88 -177.23 -177.57 9.887 5.725 3.935 2.978 2.386 1.984 1.694 1.474 1.302 1.163 1.048 0.952 0.870 0.800 0.738 0.684 0.637 0.594 0.556 0.521 0.490 122.68 103.61 94.21 87.84 82.79 78.43 74.50 70.85 67.41 64.14 61.02 58.01 55.13 52.35 49.67 47.09 44.61 42.22 39.92 37.70 35.58 0.026 0.030 0.031 0.031 0.031 0.030 0.030 0.029 0.029 0.028 0.028 0.027 0.026 0.026 0.025 0.025 0.024 0.024 0.024 0.024 0.023 35.10 19.75 13.81 10.87 9.25 8.38 8.00 7.98 8.27 8.84 9.67 10.77 12.13 13.74 15.62 17.75 20.12 22.72 25.51 28.46 31.54 0.533 0.591 0.608 0.617 0.625 0.633 0.641 0.650 0.659 0.668 0.678 0.688 0.698 0.708 0.718 0.728 0.738 0.748 0.757 0.767 0.776 -163.66 -168.52 -170.21 -170.66 -170.60 -170.31 -169.91 -169.49 -169.07 -168.69 -168.35 -168.07 -167.84 -167.66 -167.54 -167.47 -167.44 -167.46 -167.52 -167.61 -167.73 VDS = 8 V and 30% IDSS at T A = 25C 6 TriQuint Semiconductor, Inc. * Texas Facilities * (972) 995-8465 * www.triquint.com TGF4250-EEU MECHANICAL DRAWING 1.334 R/C*** 1.181 5 11 0.999 1 7 0.759 2 8 0.519 3 9 0.279 4 10 12 0.096 6 0.0 0.0 0.098 0.286 0.468 0.572 Units: millimeters Thickness: 0.102 Chip size 0.0508 Bond Bond Bond Bond Bond Bond pad pad pad pad pad pad 1 2 3 4 5 6 (gate): (gate): (gate): (gate): (gate): (gate): 0.075 0.075 0.075 0.075 0.075 0.075 x x x x x x 0.075 0.075 0.075 0.075 0.075* 0.075* Bond pad 7 (drain): 0.089 x 0.089 Bond pad 8 (drain): 0.102 x 0.089 Bond pad 9 (drain): 0.102 x 0.089 Bond pad 10 (drain): 0.089 x 0.089 Bond pad 11 (drain): 0.089 x 0.089** Bond pad 12 (drain): 0.089 x 0.089** Minimum connections to Bond Pads 1 to 4 and 7 to 10. Sources are connected to backside metalization. * Gate pad used when paralleling HFETS. ** Drain pad used when paralleling HFETS. *** R/C denotes the row, column location of the device on the wafer . NOTES Gate bias supplies should be designed to sink or source gate current. The magnitude and direction of the gate current is a function of bias point, load impedance, and drive level. Space qualification is in progress; contact TriQuint for details. TriQuint Semiconductor, Inc. * Texas Facilities * (972) 995-8465 * www.triquint.com 7 |
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